Electronic Design and Automation

FPGA Vs ASIC

2006-11-24T18:33:00.000+05:30

Remember Structured ASICs? They were gate arrays reborn: master slices with memory, common peripherals or functions and large arrays of metal-configurable logic pre-diffused, waiting for the last few metal masks to implement the customer’s design in weeks. Real ASICs might be dieing, but Structured ASICs were going to fit perfectly into that big empty space between FPGAs and fully cell-based design, gradually taking up more and more design starts from both alternatives. Many in the press, including this reporter, enthusiastically reported on their rosy future.

But it didn’t work out that way. This year LSI Logic, one of the early proponents, bailed out of the Structured ASIC market while in the process of reinventing itself. Neither NEC nor Fujitsu, both also originally bullish on the devices, are still offering Structured ASICs but no longer emphasize them in their discussions with the press. So is it the Structured ASIC that is dead now?

Nothing would please the FPGA industry more. Structured ASICs occupy the space into which the FPGA business was supposed to grow most rapidly—the mid-range of capacity and performance that defined the practical low end of the ASIC market. Without Structured ASICs buzzing about, the FPGA guys should see their dreams of ASIC conquest coming true. But this scenario hasn’t exactly come about either. FPGAs remain stubbornly impacted in the high-end prototyping/verification market and the low-end logic consolidation area.

So what is going on? One answer is that the SoC market has changed profoundly over the last few years. The number of SoC design starts has declined, perhaps, but the centrality of the cell-based flow, made easier by increasingly effective techniques for finding, evaluating and assembling third-party IP, continues. And as product differentiation has shifted from hardware to software, the availability of ASSPs has for many design teams rendered SoC design unnecessary.

Also, note that a couple of Structured ASIC vendors are doing just fine, thank you. AMI Semiconductor is still doing a strong FPGA conversion business using Structured ASICs as their target. And Faraday Technology is very happy with their results selling Structured ASICs to ASSP developers.

The real answer may be that Structured ASICs are in fact alive and well. In companies that emphasize their cell-based and foundry offerings, the structured devices have served as a selling tool and an important, if little-used, intermediate step in what often ends up being a full-on cell-based design. In much of the ASSP industry structured techniques, whether internally developed or from Structured ASIC vendors, have become central to the design flow. If there is a challenge to the approach, it is from the growing sophistication with which SoC designers are wedding themselves to the third-party IP industry, learning to assemble big silicon-tested blocks into complex chips with short design cycles.

ANTLR to run on Cygwin and GCJ

2006-10-16T17:53:00.000+05:30

I've been trying to get ANTLR 2.7.4 to run under Cygwin with GCJ. After trying to piece information together, I've finally found a recipe that makes it work.

For those who don't know ANTLR: it's a replacement for the lex/yacc combination. Unlike YACC, which is a bottom up parser, ANTLR uses a TOP-DOWN parsing approach. There is a lot of information available on the ANTLR website. If you're interested in parser generation, you certainly should have a look. My goal is to write an ANTLR compatible grammar for VHDL.

Back to the topic: ANTLR comes with a standard ./configure script. It executes fine, until, during compilation, there is an error related to AWT in directory base/antlr/debug/misc. AWT seems to be a JAVA standard library.

Some googling, resulted a link that shows how to work around the error.

I tried this, but probably because some things in my path weren't set correctly (I think), this didn't work very well either. I was able to create a libantlr.so file (see step 4 of that page), but step 5 broke down. Step 5 relies on a file called antlr/Tool.class, which doesn't exist in the ./antlr directory but in the antlr.jar file instead (a jar file is a tar-like library in which .class files can be gathered, I think.)
In the end, I got it to work by un-jarring all the files and simply bypassing the creation of a shared library.

Here's what I did: (basedir is the directory where you can find ./configure)

Install gcj (through the setup.exe on cygwin.com)
Download the tar files of the latest version of ANTLR (2.7.4 in my case) and untar it in a local directory.
Run ./configure --prefix=install dir. While we do not need to configure to compile the antlr executable, we do need it to compile the support C++ libraries. Do NOT run make after configure!
Delete AWT dependent code:
cd basedir/antlr/debug rm -fr misc
cd basedir
Un-jar all the files in the antlr.jar, back into their original position.
jar xfv antlr.jar
Compile everything into an executable
gcj --main=antlr.Tool `find antlr -name "*.class"` -o cantlr
If all is well, you will see a bunch of warnings on your screen that, I assume, you can safely ignore. The end result is a file called cantlr.exe).
Test the executable by running it (./cantlr). You should see a bunch of lines with program information.
Move this file to a place somewhere in your path (e.g. /usr/local/bin)

At this point, we have created that main executable that will convert a .g grammar file into a set of Java, C# or C++ files. These newly generated files, however, rely on base classes that are also part of the ANTLR distribution. For C++, we need to build a library that contains the compiled based classes.

cd basedir/lib/cpp
Build the C++ library. This step won't work if you previously didn't run ./configure.
make
If everything went fine, then the ./src directory will contain a file called libantlr.a. Now install the library and include files to the place that was originally indicated during the ./configure step.
make install

The next step is to test if now have a fully working system.

cd basedir/examples/cpp/calc
The standard Makefile will not know where to find the antlr executable. As a work around, just generate all files by manually invoking antlr.
cantlr calc.g
A set of C++ files will now be generated.
make
If everything went fine, you will now see a fresh set of executables!

This is how I got the system work for me while using GCJ and Cygwin. I'm pretty sure that the same procedure will also work in a Solaris or Linux environment...

Tattooing game for PDAs/phones & controlling race cars with sounds

2006-08-02T11:48:00.000+05:30

Assembly 2006 (computer fest in Finland) posted their game entries to download and check out, my favorite is "TattooFrenzy" by Fingersoft - "Draw tattoos with your PocketPC touch screen. Customers enter your tattoo place and they each want a specific tattoo. You should draw it fast and accurately enough, or the customer will surely kick your a55!" [via] - Link. Also, "Racing pitch" lets you control a car by making race car sounds in to the mic.

Pictured here, TatooFrenzy on my phone (you use the stylus as a needle)...

QuoteBot: Wet Dreams and Nano-Hype

2006-05-12T15:19:00.000+05:30

When the Twenty-First Century Nanotechnology R&D bill was being debated, it included a call for a comprehensive SEIN (Societal and Ethical Implications of Nanotechnology) center. (Howard) Lovy called a SEIN center "a philosophy and communications department head's wet dream come true," and I have little doubt he was describing me -- and on one level he is correct. For far too long, scientists have simply ignored the role of the public.

David Berube, writing in his book, Nano-Hype

Backgrounder
Clash of the Nanotech Titans

New chip for better performance and battery life

2006-04-24T09:48:00.000+05:30

Anyone who uses a cell phone or a WiFi laptop knows the irritation of a dead-battery surprise. But now researchers at the University of Rochester have broken a barrier in wireless chip design that uses a tenth as much battery power as current designs and, better yet, will use much less in emerging wireless devices of the future.

Hui Wu, professor of electrical and computer engineering at the University of Rochester, a pioneer in a circuit design called an “injection locked frequency divider,” or ILFD, has solved the last hurdle to making the new method work. Wireless chip manufacturers have been aware of ILFD and its ability to ensure accurate data transfer using much less energy than traditional digital methods, but the technique had two fatal flaws: it could not handle a wide range of frequencies, and could not ensure a fine enough resolution within that range. Wu, together with Ali Hajimiri, associate professor of electrical engineering at California Institute of Technology, surmounted the first problem in 2001, and has now found a solution for the latter.

Wu’s new design makes the practical application of ILFDs possible. He introduced a new topology into this circuitry—instead of the old three-transistor design, his has five transistors—creating what he calls “differential mixing.” The new circuitry topology allows the ILFD to divide by three as well as two.

This tiny change has huge ramifications. A circuit design that can divide by two or three can, for instance, divide 9,999 clock pulses by two, and the 10,000th by 3, giving an average of 2.0001, which could be the frequency at which the cell phone is trying to communicate. Should the phone need to communicate at 2.0002 gigahertz, the ILFD could divide 9,998 clock pulses by two, and the 9,999th and 10,000th by three, yielding an average of 2.0002. By varying how many clock pulses are divided by two or by three, any frequency can be selected, making the power-saving ILFD method viable for the first time.

Analog & Chip Industry in india, Quality Concerns

2006-04-11T10:23:00.000+05:30

India is witnessing an inflow of chip design from Multinatinals.
Existing companies have been increasing their staff strength in India,
while others are expanding in India.

This has resulted in a shortage of quality manpower & critical mass to
maintain.

Companies keep hiring from existing companies and this has impacted the
project execution in those companies who lost their staff.
The new design centre takes time to kick off & they just try to keep
the hired engrs without benifiting from them.

This has created shortage of manpower in Analog design. Many companies have
just one expereinced engineer.With skilled people divided among companies &
without critical mass in many companies,Indian Industry as a whole is suffering.
Corporates need to take a more wider & responsible view of the situation otherwise,
It would become more of a "trainee" industry where, trained people (1yr exp) keep on
doing job hopping & getting salary hikes without delivering projects anywhere.

Call for Papers

2006-03-06T16:05:00.000+05:30

Xilinx unveils free RPR MAC reference design for Virtex-4 FPGAs

2005-12-03T20:33:00.000+05:30

Xilinx Inc. announced a free RPR MAC reference design for use with its Virtex-4 family of domain-optimized FPGAs. This new solution implements a complete RPR MAC supporting all key features of the IEEE 802.17 specification, including MAC data path for east and west, Fairness, Topology, Protection and OAM. According to Xilinx, flexibility is provided through support for 1G, 2.5G and 10G rates, various PHY side interfaces (GMII, SPI-3, SPI-4.2, XAUI and XGMII), memory interfaces, and a host of client interfaces. High availability is achieved via built-in functionality for equipment protection/redundancy.

The Virtex-4 family is revolutionizing the fundamentals of FPGA economics, said the company. With three application-domain-optimized platforms and a selection of seventeen devices, this FPGA family promises to deliver breakthrough performance at the lowest cost and offer a compelling alternative to ASICs and ASSPs.

The RPR MAC reference design is available free of charge at Xilinx's website. The design package includes the design netlist, software drivers and complete documentation including a compliance matrix.

Organ Repair

2005-11-17T12:14:00.000+05:30

Scientists are working on a new way to repair organs. As this ScienCentral News video reports, they're trying to build replacement parts using a three-dimensional printer.

Printing Organs

At the bottom of the basement stairs in the physics building at the University of Missouri-Columbia, and just to the left, there is a brown steel door marked "Research." Behind it fluorescent lights hum, a miniature guillotine clicks, and a printer paces back and forth.

But this is no mad scientist's den, nor is it a traditional physics laboratory. Here researchers, led by biological physicist Gabor Forgacs are developing a three-dimensional printing technique that may one day be used to engineer replacement parts for worn-out or diseased organs. It is a method they hope will ultimately reduce the number of whole organ transplants needed by providing patients with just the spare parts they need.

"In twenty years," says University of Washington Department of Surgery burn specialist Nicole Gibran, "This may be what we're doing."

"The primary manifestation of this technology," says Forgacs, "perhaps in practice, will be grafts, skin grafts, vascular grafts, and the like, but not necessarily complicated organs as in livers or hearts."
Read more

Fountain Pen Revival

2005-11-14T20:45:00.000+05:30

What was old is now new again. Who would have thought that the fountain pen would be used again for modern cutting edge technology, but that is just what is happening at Northwestern University in Chicago. Researchers have recently re-invented the fountain pen on a microscale level by developing a pen that can write on the molecular level!

The "nanoscale fountain pen" was constructed using microfabrication techniques based on silicon fab technology. The research behind this device stems from dip pen nanolithography (DPN), which combines microelectronics fabrication and microfluidics to achieve molecular manipulation at the nanoscale level.

Where do electronics and photonics meet?

2005-11-07T11:04:00.000+05:30

For 50 years we have seen a continual progression of smaller and more powerful electronic devices. Till today it seems everything you touch includes some sort of electronic device. It seems likely that may be changing. There is considerable research going on into photonics. Essentially replacing electrons with photons as the mechanism for all these activities. It seems that chips designed around photonics would use less energy and carry more data and work directly with fiber optic comminications networks. The trick is how to interface these photonic devices with electronic devices for the things that photonics are not able to do. Researchers at Cornell may have developed the first part of an answer. They have developed a silicon based device that can use an electronic signal to create a photonic signal. We are talking about nanostructures here. So check it out.

DACs jammed with functionality

2005-11-05T12:45:00.000+05:30

Multichannel digital-to-analog converters (DACs) from Analog Devices Inc. (ADI) are said to pack the highest concentration of analog signal processing performance in a single chip.
Developed using ADI's patented iCMOS process, the eight monolithic DACs extend the company's dense D/A CONVERTER family offering, combining up to 40 channels, high accuracy and ±10V range, in a tiny footprint.

ADI's iCMOS process combines high-voltage silicon with submicron CMOS and complementary bipolar technologies.

Programmable on-chip features, such as calibration registers and automatic shutdown, ensure system reliability in harsh, high voltage industrial environments, while simplifying board layout, said Mike Britchfield, ADI's product line director, precision signal processing. "These devices satisfy the needs of today's systems designers trying to squeeze more and more functionality into smaller board space, particularly in ATE (pin-electronics), optical networking (switches, VOAs) and precision instrumentation applications (oscilloscopes, data generators, industrial I/O cards)," he said.

The AD5362 is said to be the first 8-channel D/A converter with bipolar voltage outputs, 16-bit differential nonlinearity (DNL) and 14-bit integral nonlinearity (INL). In addition, the D/A converter incorporates individual user-programmable offset and gain registers per channel, enabling board designers to calibrate their systems and compensate for signal errors that may occur elsewhere in the signal chain.

A 50MHz SPI-compatible serial interface offers group addressing, facilitating fast updating of multiple D/A converter channels. It also offers flexible diagnostic features, including readback and packet error checking (PEC).

The AD5362 is available in an 8-by-8mm 56-lead LFCSP. Other members of the pin-compatible AD536x family offer higher channel (16-channel) or lower resolution (14-bit) alternatives.

The AD5370 is a similar 40-channel version. A programmable 20V output span provides flexibility in customizing voltage output levels. For even greater flexibility, the device is divided into five groups of eight D/A converters. A separate input pin is also provided for each group to enable remote ground sensing. Furthermore, the AD5370 has two voltage reference pins and two offset D/A converters, enabling the user to set different output voltage ranges.

The AD536x and AD537x D/A converters are sampling now, with production planned for June 2006.

Pricing for the AD5362/AD5363 and AD5370 D/A converters ranges from $19.50 to $62.90 each, depending on configurations, in 1,000-piece quantities.

Structured ASIC demand rising, says study

2005-11-02T12:07:00.000+05:30

Innovation in the IC industry combined with increasing demand for high-performance electronic systems is driving demand for structured ASICs, according to a study by Frost and Sullivan.

"Structured ASICs are proving to be highly promising components for next-generation devices and combine the performance/cost advantage of standard-cell ASICs and the low-risk nature of FPGAs while dramatically simplifying the design process," said Sivakumar Muthuramalingam, research analyst at Frost and Sullivan (New York).

According to Muthuramalingam, structured ASICs can slash NRE costs by over 85 percent in derivative chips and are set to become a crucial element in deep sub-micron (DSM) designs. "A significant percent of FPGA design wins could now be lost to structured ASICs that lowers cost and time to market, while increasing performance," he said.

Though the benefits of structured ASICs are known, researchers still need to address issues such as cross talk and signal integrity when implementing designs at DSM levels. In the more advanced process nodes, power leakage is a serious issue that needs to be resolved. Another challenge is in generating awareness and popularizing structured ASICs across a diverse range of end-user applications.

The target markets for structured ASICs include telecommunications, data storage and digital computing/networking that demand high performance, but require modest production volumes.
Source: EE Times

First Nano Car Designed

2005-10-30T11:06:00.000+05:30

A group of scientists hailing from Rice University hav now claimed to have developed the world’s smallest car, the nanocar. This driving body has now been described in a research paper that says the car contains a chassis, axles and four buckyball wheels. More details about this nanocar is expected to be published soon in an upcoming issue of the Nano Letters journal. These single-molecule vehicles have a measurement specification of just 4x3 nanometers, this is just a bit wider than a strand of DNA. The car has four buckyball wheels made of 60 atoms apiece and connected to four independently rotating axles and an organic chemical chassis. The developers of this car look at it as some sort of landmark in molecule scale manufacturing. James M Tour, a lead researcher of the project commented, "The synthesis and testing of nanocars and other molecular machines is providing critical insight in our investigations of bottom-up molecular manufacturing. We'd eventually like to move objects and do work in a controlled fashion on the molecular scale, and these vehicles are great test beds for that. They¹re helping us learn the ground rules." The car was evolved after an extensive eight years of. It’s main function in the future will be to carry nano-sized payloads from point A to B.

The Innerworkings of the Transistor

2005-10-27T11:05:00.000+05:30

Since transistors are used everywhere today from Computers to Microwaves to Electronic giftcards I thought It might be a good idea to write up an article on how they work to elimate any confusing ideas a begginger in electronics might have.

Now on to how a transistor works. Here is a diagram that I will use to explain this all.

Collector-----

+
+
Gate----------
+
+

Emitter-------

The gate is just another name for the base. Transistors all have a V-be voltage this is the voltage that it takes to turn the transistor on. After it is on it can operate in different modes. Cutoff. This mode is when the voltage through the base and emitter is less than the V-be voltage needed to turn the transistor on. Forward Active. This mode is what amplifiers use in this mode a change in the base current results in a change in the current that is allowed to pass from the collector to the emmiter. The change is a multiple of beta. Most of the time beta is around 100 so the current that flows from the collector to the emitter is 100 times greater than the current going from the base to the emitter. Saturation. This mode is when more current from the base to the emitter produce little change in the current from the collector to the emitter. Saturation is most often used in things that need transistors to switch things on and off.

As you can see here you have a gate by with you can tell thats its going to control the Collector and Emitter. Well when you have a large voltage behind the Collector it collects it and when a small voltage is passed to the Gate it opens the path way for the large voltage can get through and go out of the transistor through the Emitter. In a PNP transistor The N is the gate since its the middle letter and one P is the collector and the other is the Emitter. WHen you apply a voltage to the gate the gate in a PNP turns from a N into a P which unblocks the voltage behind it and in a NPN the gate turns from P to N so the easyest way to know which way your gate is turning is to look at the two outside letters since the gate needs to be the same as them to allow a voltage to go through. Since they both work the same way what would be the sence of having both NPN and PNP transistors, the NPN transistors are for slower electronics that hobbists would use well PNP are much faster transistors that are uses in computers.

One of the problems that we have with transistors is that they can easly be killed by static discharges making a corona of high voltage around the gate with permantly turns the gate on. This is allowed because of Kirchhoff's Voltage law and the weak dielectric strenght between the layers of P's and N's

Breakdown is caused when one tryed to send a reverse voltage through the gate. When a high enough reveresed voltage is applyed the skin effect occures and the transisotr can literaly explode from surface heating.

Transistors like resistors and Inductors can be damage by EMP (Electro Mangetic Pulse) with is basicly a strong mangetic feild the grables up the atoms inside of the electonic parts. Caused by a Induced charge on the dielectics which would just turn your part into a jumper wire.

Transistor Flow Control

2005-10-23T11:05:00.000+05:30

At the heart of modern electronics are transistors, which act like valves to direct the flow of electrons. Now researchers at the University of California at Berkeley have created the first transistors that electrically control molecules instead. By connecting them to microscopic test tubes and petri dishes, these nanoscale transistors could lead to labs-on-a-chip that work without moving parts.
Much as 30-ton computers shrank over decades to microchip size, investigators are now miniaturizing labs to run millions of experiments simultaneously and dramatically speed analysis of DNA, proteins and other molecules. Although valves and pumps exist to control flow in microfluidic channels, they are not easy to miniaturize further for use on nanometer levels, says Berkeley mechanical engineer Arun Majumdar.
Read more

Catalyzing Nanotechnology

2005-10-13T11:03:00.000+05:30

As scientists and engineers continue to make progress in the realm of nanotechnology, new tools become necessary to synthesize more complicated structures on such tiny scales. UC Berkeley chemical engineer Alexander Katz is developing several techniques to fashion structures that spur specific chemical reactions but are as small as a single nanometer. His processes range from a cookie-cutter templating technique to methods directly inspired by Mother Nature. Eventually, the materials that Katz and his collaborators discover could speed the development of nanoscale electronic components for future computers and related memory systems.

Alexander Katz and his colleagues have a U.S. patent on one of their methods to bind functional groups on surfaces discovered at Berkeley, with two others currently pending.
"Standard lithographic etching used to make microprocessors is certainly able to create mechanical features of the right size and shape," Katz explains. "But as these features become smaller in the future, what becomes as important as their size and shape is local arrangement of chemical functional groups. How can we organize these groups and the environment surrounding them in solids?"
Because of their small size, the structures that Katz's research group synthesizes can be used as active catalytic sites for causing chemical transformations to occur. Chemists use catalysts to speed the rate of chemical reactions. The catalyst acts as a pathway between the reactants and the end product that requires less of an energetic barrier than the transformation would take otherwise. Because the nanoscale order in Katz's sites can interact with a reactant molecule specifically, these sites can induce chemical reactions with great selectivity. For instance, some of Katz's sites can steer the product of a chemical reaction to be one or another molecule, depending on the functional group arrangement. The most proficient examples of how elaborate organization of functional groups can affect catalysis can be found inside of each of us.
"The functional groups that keep us alive consist of relatively simple building blocks," Katz says. "But the way they're assembled is intricate. It's that assembly that imparts elaborate catalytic properties."
Molecular imprinting in silica is a method Katz and his colleagues developed to achieve nanoscale functional group organization in solids. The researchers take a particular molecule and mold silica around it. The molecule is then removed but chemical functional groups are left attached to the inside of the mold. The end result is a solid, visually not unlike an ordinary piece of glass, but actually riddled with miniscule imprinted pores. Organic molecules bind inside these pores where the imprinted functional groups promote a chemical reaction.
The researchers have also explored a method to imprint bulk silica with particle templates as large as 15 nanometers. Rather than organize several functional groups at a time, the synthesis of nanoparticle building blocks for bulk silica imprinting is ideal for organizing thousands of functional groups at once, Katz says.
The process is similar to the single-molecule imprinting, but in this case a nanoparticle with a functional group organized on its surface is bound in the silica. After the nanoparticle core is removed, the organized functional groups remain immobilized in the structure.
In another technique that Katz and his coworkers discovered, bowl-shaped functional groups are grafted to the surface of a piece of silica. The functional groups act as one nanometer-sized "pocket" that only allows certain catalytic reactions to occur. The rim of the pocket and the surface of the silica can also be altered to affect the catalyst properties.
"The mechanism and the selectivity of these reactions, in addition to catalyst activity, can be dictated by our ability to organize chemical functional groups in solids," Katz explains. "All of our efforts are about taking something ordinary, like these functional groups, and enabling them to do extraordinary things when arranged cooperatively within a nanoscale site."
Courtesy:Science matters

Call for Papers is Now Open for User2User 2006!

2005-09-15T11:02:00.000+05:30

Abstract submission deadline: Friday, October 28, 2005 at 5:00 pm PDT - Submit an abstract today
Conference: May 3 - 5, 2006Pre-Conference Workshops: May 2, 2006Locations: San Jose Marriott and
User2User is the annual Mentor Graphics International User Conference. This highly interactive, in-depth technical conference focuses on the needs of the entire Mentor Graphics user community and draws attendees from around the world. Our primary goal is to deliver immediately useful technical content.
The 2006 conference will again offer a wide range of workshops, technical presentations, and networking opportunities. We encourage you to share your best practices, success stories, and lessons learned.
Submitting an Abstract is Easy
Review the conference technical tracks and suggested topics. Choose one of these topics, a related topic, or come up with your own.
Fill out and submit the abstract submission form with a short (150 words) abstract by October 28, 2005 at 5:00pm PDT (or October 7, 2005 at 5:00pm PDT to be eligible for the early submission awards).
Submit Early - Get a T-shirt and Maybe More!
More than 200 abstracts were submitted for User2User 2005. To give the Conference Advisory Board (CAB) ample time to review submissions, all those submitting abstracts by Friday, October 7, 2005 at 5:00pm PDT, will receive a special edition t-shirt, plus be entered in a drawing to receive one of the following items:

Best Paper Awards
A Best Paper award of $1,000 USD will be given in each conference track. Click here for complete details.
For additional information please contact Jen Chausse (Jennifer_chausse@mentor.com or 720-494-1144) or Gordon Sorensen (Gordon_sorensen@mentor.com or 503-685-7757)

Doors 'open' to hardware

2005-09-01T11:01:00.000+05:30

Is "open" hardware a disruptive technology that will foster the kind of collaboration that Linux brought to the software world?
Despite the recent demise of one prominent open-source programmable-logic effort, advocates think so. Given the increasingly prohibitive costs of developing hardware from scratch, open hardware is an attractive possibility. But the road is not easy, and new business models will be needed to support it.
At the Electronic Design Processes workshop, Juan-Antonio Carballo, partner in IBM's venture-capital group, made an eloquent pitch for open hardware. "The open-source model is quickly extending from software to hardware, and it will provide a similar swell of collaborative innovation," he said.
The word "open" has various meanings, Carballo explained. It includes, but is not limited to, open source, where specifications or source code are freely available and can be modified by a community of users. It could also mean that the hardware details can be viewed, but not modified. And it does not necessarily mean that open hardware, or designs that contain it, are free of charge.
The open-hardware movement suffered a blow in late April when STMicroelectronics pulled the plug on its Generalized Open Source Programmable Logic initiative. That effort was launched last year in India, with the stated goal of becoming the "Linux of the semiconductor world." While never fully opened to the public, it was seeking "qualified contributors" who would have access to EDA source code and to hardware and software intellectual property.
Still, there are other open-hardware efforts. One (www.power.org) represents a community of developers, tool providers and manufacturers who are developing standards and applications around IBM's Power Architecture. The Power.org mission statement calls for an "open-standard hardware development platform for the electronics industry," with open standards, specifications, guidelines and best practices.
An active community is developing around open-source IP cores. The www.opencores.org Website lists a number of projects, including cores for arithmetic functions, DSP, communications protocols, memory and microprocessors. An OpenTech CD-ROM compiles several hundred open-source EDA software programs and hardware designs.
One pointed question is how to make money from open hardware. The answer may be similar to that in the Linux world: support and value-added services. At the Opencores site, OpenTech creator Jamil Khatib recently launched OpenSupport, a partner program designed to provide commercial support for open-source designs.
- Richard Goering
EE Times

National Semiconductor Boosts FPGA Signal Integrity

2005-08-18T10:59:00.000+05:30

National Semiconductor Corporation (NYSE: NSM) today introduced two new low-power, high-performance buffer/repeaters for its industry-leading portfolio of LVDS (low-voltage differential signaling) products.

National's DS90LV004 and SCAN90004 1.5 Gbps, four-channel buffers are the first to include configurable output pre-emphasis, hot-plug protection and 15 kV of electro-static discharge (ESD) protection. The devices boost the signal integrity of field-programmable gate arrays (FPGAs) and application specific integrated circuits (ASIC) across backplanes and cables in telecom, datacom, industrial, medical, automotive and office imaging applications. For designers who want to implement system-level test, the SCAN90004 features IEEE 1149.6 (JTAG) testability.

"The DS90LV004 and SCAN90004 dramatically improve the performance of a wide variety of designs driving high-speed signals," said Jeff Waters, product line director for the Interface division at National. "In FPGA- and ASIC-based designs, for example, these buffers can provide ESD protection up to 15 kV and deliver higher-speed and longer-reach signals over lower-cost cables and backplanes."

Technical Features of the DS90LV004 and SCAN90004 LVDS Buffer/Repeaters

The four-channel DS90LV004 drives up to four LVDS clock and/or data channels over common backplanes or simple cable configurations. The wide differential input range easily interfaces to LVDS, low voltage positive emitter-coupled logic (LVPECL) or current mode logic (CML) input levels and the output levels are fully LVDS compliant. The DS90LV004 operates at data rates up to 1.5 Gbps and includes configurable output pre-emphasis that allows the designer to "overdrive" the outputs to compensate for a lossy interconnect. The DS90LV004 also features the industry's highest 15 kV of ESD protection for maximum isolation of expensive FPGAs, ASICs and other onboard components. In power-sensitive applications, the power-down mode is useful in minimizing power consumption when all four channels of a single device are not active, as in redundancy applications.

The SCAN90004 has the same features as the DS90LV004, and also includes IEEE standard 1149.1 and 1149.6 (JTAG) testability to verify high-speed differential connections in the system. These JTAG-accessible features extend the capability of an existing system or board-level JTAG bus to high-speed mixed-signal environments.

For more information on the DS90LV004 and SCAN90004 or to order samples and an evaluation board, visit http://www.national.com/pf/DS/DS90LV004.html and http://www.national.com/pf/SC/SCAN90004.html . For more information on National's interface products, visit http://lvds.national.com . An on-demand online seminar, "Boosting FPGA and CPLD Interface Performance for Off-board Data Transmission" is available for viewing at http://www.national.com/onlineseminar/

Gap Between Analog and Digital Designers

2005-08-07T10:57:00.000+05:30

In the past, the gap between analog and digital designers has been large. With the adoption of new DSM processes, the gap is getting smaller. The analog (transistor level IP folks also) have until recently allowed this encroachment without much concern or frustration. In a lot of cases, they were actually happy to have to dish off the long run time “in-situ” simulations to confirm the application of the design block in the middle of the “digital logic stuff”.
The digital designers, have also been happy in a safe static timing analysis (STA) and transient analysis world that has been confined to the time domain. The results were definitively interpretable and scripts could even be created in some cases, to read the results for you and let you know if it passed on a GO/NO GO condition.
Recent industry events have shown that the world is not so simple now – AC and Frequency domain analysis – One the LAST bastions of exclusivity to the analog gurus is NOW an SOC analysis technique. Mixed signal, RF, wireless, high speed interfaces, sensor interfaces, clocks, PLLs, and power grids are NOW all being looked by AC modeling tools as required signoff in the digital design flow.
This impacts the design world a lot more than people think. First it requires BOTH quantitative and qualitative interpretation of results to know what “it is good” means. Second, the models that represent these views are NOT present in .LIB files so in-house correlation and qualification of results is required – even if you bought the IP from a known good vendor. And mostly, for design group to succeed, the analog and digital guys have to get together and actually communicate on a COOPERATIVE not COMPETATIVE basis to make sure the design works. It is not practical with today’s TTM pressures, to require the analog designers to learn all about digital assertions, constraints and synthesis or to make the HDL coders and architecture folks learn about phase, harmonics and numerical idiosyncrasies of the device level models and simulators.
A lot of talk in the industry has been about the rate of adoption of the these new process nodes and the economic justifications behind migration – the bigger discussion should be – can the industry create a positive work environment and updated design methodology that actually encourages/empowers the Engineer to perform the work that they believe in and receives recognition for – or we are doom to fail to grow the industry as it will become just a bunch of “tool operators” who do not know WHY they are using item 4 from the third pull down menu on the left.

Very-large-scale integration

2005-08-02T10:56:00.000+05:30

Very-large-scale integration (VLSI) of systems of transistor-based
circuits into integrated circuits on a single chip first occurred in
the 1980s as part of the semiconductor and communication technologies
that were being developed.

The first semiconductor chips held one transistor each. Subsequent
advances added more and more transistors, and as a consequence more
individual functions or systems were integrated over time. The
microprocessor is a VLSI device.

The first "generation" of computers relied on vacuum tubes. Then came
discrete semiconductor devices, followed by integrated circuits. The
first Small-Scale Integration (SSI) ICs had small numbers of devices on
a single chip - diodes, transistors, resistors and capacitors (no
inductors though), making it possible to fabricate one or more logic
gates on a single device. The fourth generation consisted of
Large-Scale Integration (LSI), i.e. systems with at least a thousand
logic gates. The natural successor to LSI was VLSI (many tens of
thousands of gates on a single chip). Current technology has moved far
past this mark and today's microprocessors have many million gates and
hundreds of millions of individual transistors.

As of mid-2004, billion-transistor processors are not yet economically
feasible for most uses, but they are achievable in laboratory settings,
and they are clearly on the horizon as semiconductor fabrication moves
from the current generation of 90 nanometer (90nm) processes to the
next 65nm and 45nm generations.

At one time, there was an effort to name and calibrate various levels
of large-scale integration above VLSI. Terms like Ultra-large-scale
Integration (ULSI) were used. But the huge number of gates and
transistors available on common devices has rendered such fine
distinctions moot. Terms suggesting more-than-VLSI levels of
integration are no longer in widespread use. Even VLSI is now somewhat
quaint, given the common assumption that all microprocessors are VLSI
or better.

VLSI Conferences

DAC - Design Automation Conference CAS - IEEE Circuits and Systems Conferences ICSVLSI- IEEE Computer Society Annual Symposium on VLSI EDS - IEEE EDS Meetings Calendar EDS - IEEE EDS Sponsored, Cosponsored & Topical Conferences IEDM - IEEE International Electron Devices Meeting

VLSI Journals

ED - IEEE Transactions on Electron Devices
EDL - IEEE Electron Device Letters
CAD - IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems
JSSC - IEEE Journal of Solid-State Circuits
VLSI - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CAS II - IEEE Transactions on Circuits and Systems II: Analogy and
Digital Signal Processing
SM - IEEE Transactions on Semiconductor Manufacturing
SSE - Solid-State Electronics
SST - Solid-State Technology
TCAD - Journal of Technology Computer-Aided Design

Further reading

Carver Mead, Lynn Conway, Introduction to VLSI Systems (Addison-Wesley,
1980)
Neil H.E. Weste, David Harris, CMOS VLSI Design (Addison-Wesley, 3rd
Edition)