FPGA Vs ASIC

Remember Structured ASICs? They were gate arrays reborn: master slices with memory, common peripherals or functions and large arrays of metal-configurable logic pre-diffused, waiting for the last few metal masks to implement the customer’s design in weeks. Real ASICs might be dieing, but Structured ASICs were going to fit perfectly into that big empty space between FPGAs and fully cell-based design, gradually taking up more and more design starts from both alternatives. Many in the press, including this reporter, enthusiastically reported on their rosy future.

But it didn’t work out that way. This year LSI Logic, one of the early proponents, bailed out of the Structured ASIC market while in the process of reinventing itself. Neither NEC nor Fujitsu, both also originally bullish on the devices, are still offering Structured ASICs but no longer emphasize them in their discussions with the press. So is it the Structured ASIC that is dead now?

Nothing would please the FPGA industry more. Structured ASICs occupy the space into which the FPGA business was supposed to grow most rapidly—the mid-range of capacity and performance that defined the practical low end of the ASIC market. Without Structured ASICs buzzing about, the FPGA guys should see their dreams of ASIC conquest coming true. But this scenario hasn’t exactly come about either. FPGAs remain stubbornly impacted in the high-end prototyping/verification market and the low-end logic consolidation area.

So what is going on? One answer is that the SoC market has changed profoundly over the last few years. The number of SoC design starts has declined, perhaps, but the centrality of the cell-based flow, made easier by increasingly effective techniques for finding, evaluating and assembling third-party IP, continues. And as product differentiation has shifted from hardware to software, the availability of ASSPs has for many design teams rendered SoC design unnecessary.

Also, note that a couple of Structured ASIC vendors are doing just fine, thank you. AMI Semiconductor is still doing a strong FPGA conversion business using Structured ASICs as their target. And Faraday Technology is very happy with their results selling Structured ASICs to ASSP developers.

The real answer may be that Structured ASICs are in fact alive and well. In companies that emphasize their cell-based and foundry offerings, the structured devices have served as a selling tool and an important, if little-used, intermediate step in what often ends up being a full-on cell-based design. In much of the ASSP industry structured techniques, whether internally developed or from Structured ASIC vendors, have become central to the design flow. If there is a challenge to the approach, it is from the growing sophistication with which SoC designers are wedding themselves to the third-party IP industry, learning to assemble big silicon-tested blocks into complex chips with short design cycles.

ANTLR to run on Cygwin and GCJ

I've been trying to get ANTLR 2.7.4 to run under Cygwin with GCJ. After trying to piece information together, I've finally found a recipe that makes it work.

For those who don't know ANTLR: it's a replacement for the lex/yacc combination. Unlike YACC, which is a bottom up parser, ANTLR uses a TOP-DOWN parsing approach. There is a lot of information available on the ANTLR website. If you're interested in parser generation, you certainly should have a look. My goal is to write an ANTLR compatible grammar for VHDL.

Back to the topic: ANTLR comes with a standard ./configure script. It executes fine, until, during compilation, there is an error related to AWT in directory base/antlr/debug/misc. AWT seems to be a JAVA standard library.

Some googling, resulted a link that shows how to work around the error.

I tried this, but probably because some things in my path weren't set correctly (I think), this didn't work very well either. I was able to create a libantlr.so file (see step 4 of that page), but step 5 broke down. Step 5 relies on a file called antlr/Tool.class, which doesn't exist in the ./antlr directory but in the antlr.jar file instead (a jar file is a tar-like library in which .class files can be gathered, I think.)
In the end, I got it to work by un-jarring all the files and simply bypassing the creation of a shared library.

Here's what I did: (basedir is the directory where you can find ./configure)

1. Install gcj (through the setup.exe on cygwin.com)
   
2. Download the tar files of the latest version of ANTLR (2.7.4 in my case) and untar it in a local directory.
   
3. Run ./configure --prefix=install dir. While we do not need to configure to compile the antlr executable, we do need it to compile the support C++ libraries. Do NOT run make after configure!
   
4. Delete AWT dependent code:
   cd basedir/antlr/debug
rm -fr misc
   
5. cd basedir
   
6. Un-jar all the files in the antlr.jar, back into their original position.
   jar xfv antlr.jar
   
7. Compile everything into an executable
   gcj --main=antlr.Tool `find antlr -name "*.class"` -o cantlr
   If all is well, you will see a bunch of warnings on your screen that, I assume, you can safely ignore. The end result is a file called cantlr.exe).
   
8. Test the executable by running it (./cantlr). You should see a bunch of lines with program information.
   
9. Move this file to a place somewhere in your path (e.g. /usr/local/bin)
   

At this point, we have created that main executable that will convert a .g grammar file into a set of Java, C# or C++ files. These newly generated files, however, rely on base classes that are also part of the ANTLR distribution. For C++, we need to build a library that contains the compiled based classes.

1. cd basedir/lib/cpp
   
2. Build the C++ library. This step won't work if you previously didn't run ./configure.
   make
   
3. If everything went fine, then the ./src directory will contain a file called libantlr.a. Now install the library and include files to the place that was originally indicated during the ./configure step.
   make install
   

The next step is to test if now have a fully working system.

1. cd basedir/examples/cpp/calc
   
2. The standard Makefile will not know where to find the antlr executable. As a work around, just generate all files by manually invoking antlr.
   cantlr calc.g
   A set of C++ files will now be generated.
   
3. make
   
4. If everything went fine, you will now see a fresh set of executables!
   

This is how I got the system work for me while using GCJ and Cygwin. I'm pretty sure that the same procedure will also work in a Solaris or Linux environment...

Tattooing game for PDAs/phones & controlling race cars with sounds

Assembly 2006 (computer fest in Finland) posted their game entries to download and check out, my favorite is "TattooFrenzy" by Fingersoft - "Draw tattoos with your PocketPC touch screen. Customers enter your tattoo place and they each want a specific tattoo. You should draw it fast and accurately enough, or the customer will surely kick your a55!" [via] - Link. Also, "Racing pitch" lets you control a car by making race car sounds in to the mic.

Pictured here, TatooFrenzy on my phone (you use the stylus as a needle)...

QuoteBot: Wet Dreams and Nano-Hype

When the Twenty-First Century Nanotechnology R&D bill was being debated, it included a call for a comprehensive SEIN (Societal and Ethical Implications of Nanotechnology) center. (Howard) Lovy called a SEIN center "a philosophy and communications department head's wet dream come true," and I have little doubt he was describing me -- and on one level he is correct. For far too long, scientists have simply ignored the role of the public.

David Berube, writing in his book, Nano-Hype

Backgrounder
Clash of the Nanotech Titans

New chip for better performance and battery life

Anyone who uses a cell phone or a WiFi laptop knows the irritation of a dead-battery surprise. But now researchers at the University of Rochester have broken a barrier in wireless chip design that uses a tenth as much battery power as current designs and, better yet, will use much less in emerging wireless devices of the future.

Hui Wu, professor of electrical and computer engineering at the University of Rochester, a pioneer in a circuit design called an “injection locked frequency divider,” or ILFD, has solved the last hurdle to making the new method work. Wireless chip manufacturers have been aware of ILFD and its ability to ensure accurate data transfer using much less energy than traditional digital methods, but the technique had two fatal flaws: it could not handle a wide range of frequencies, and could not ensure a fine enough resolution within that range. Wu, together with Ali Hajimiri, associate professor of electrical engineering at California Institute of Technology, surmounted the first problem in 2001, and has now found a solution for the latter.

Wu’s new design makes the practical application of ILFDs possible. He introduced a new topology into this circuitry—instead of the old three-transistor design, his has five transistors—creating what he calls “differential mixing.” The new circuitry topology allows the ILFD to divide by three as well as two.

This tiny change has huge ramifications. A circuit design that can divide by two or three can, for instance, divide 9,999 clock pulses by two, and the 10,000th by 3, giving an average of 2.0001, which could be the frequency at which the cell phone is trying to communicate. Should the phone need to communicate at 2.0002 gigahertz, the ILFD could divide 9,998 clock pulses by two, and the 9,999th and 10,000th by three, yielding an average of 2.0002. By varying how many clock pulses are divided by two or by three, any frequency can be selected, making the power-saving ILFD method viable for the first time.

Analog & Chip Industry in india, Quality Concerns

India is witnessing an inflow of chip design from Multinatinals.
Existing companies have been increasing their staff strength in India,
while others are expanding in India.

This has resulted in a shortage of quality manpower & critical mass to
maintain.

Companies keep hiring from existing companies and this has impacted the
project execution in those companies who lost their staff.
The new design centre takes time to kick off & they just try to keep
the hired engrs without benifiting from them.

This has created shortage of manpower in Analog design. Many companies have
just one expereinced engineer.With skilled people divided among companies &
without critical mass in many companies,Indian Industry as a whole is suffering.
Corporates need to take a more wider & responsible view of the situation otherwise,
It would become more of a "trainee" industry where, trained people (1yr exp) keep on
doing job hopping & getting salary hikes without delivering projects anywhere.

Call for Papers

Xilinx unveils free RPR MAC reference design for Virtex-4 FPGAs

Xilinx Inc. announced a free RPR MAC reference design for use with its Virtex-4 family of domain-optimized FPGAs. This new solution implements a complete RPR MAC supporting all key features of the IEEE 802.17 specification, including MAC data path for east and west, Fairness, Topology, Protection and OAM. According to Xilinx, flexibility is provided through support for 1G, 2.5G and 10G rates, various PHY side interfaces (GMII, SPI-3, SPI-4.2, XAUI and XGMII), memory interfaces, and a host of client interfaces. High availability is achieved via built-in functionality for equipment protection/redundancy.

The Virtex-4 family is revolutionizing the fundamentals of FPGA economics, said the company. With three application-domain-optimized platforms and a selection of seventeen devices, this FPGA family promises to deliver breakthrough performance at the lowest cost and offer a compelling alternative to ASICs and ASSPs.

The RPR MAC reference design is available free of charge at Xilinx's website. The design package includes the design netlist, software drivers and complete documentation including a compliance matrix.

Organ Repair

Scientists are working on a new way to repair organs. As this ScienCentral News video reports, they're trying to build replacement parts using a three-dimensional printer.

Printing Organs

At the bottom of the basement stairs in the physics building at the University of Missouri-Columbia, and just to the left, there is a brown steel door marked "Research." Behind it fluorescent lights hum, a miniature guillotine clicks, and a printer paces back and forth.

But this is no mad scientist's den, nor is it a traditional physics laboratory. Here researchers, led by biological physicist Gabor Forgacs are developing a three-dimensional printing technique that may one day be used to engineer replacement parts for worn-out or diseased organs. It is a method they hope will ultimately reduce the number of whole organ transplants needed by providing patients with just the spare parts they need.

"In twenty years," says University of Washington Department of Surgery burn specialist Nicole Gibran, "This may be what we're doing."

"The primary manifestation of this technology," says Forgacs, "perhaps in practice, will be grafts, skin grafts, vascular grafts, and the like, but not necessarily complicated organs as in livers or hearts."
Read more

Fountain Pen Revival

What was old is now new again. Who would have thought that the fountain pen would be used again for modern cutting edge technology, but that is just what is happening at Northwestern University in Chicago. Researchers have recently re-invented the fountain pen on a microscale level by developing a pen that can write on the molecular level!



The "nanoscale fountain pen" was constructed using microfabrication techniques based on silicon fab technology. The research behind this device stems from dip pen nanolithography (DPN), which combines microelectronics fabrication and microfluidics to achieve molecular manipulation at the nanoscale level.